Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9–14.3-GHz 85-fs-rms Jitter PLL Yizhuo Wang, Jiahe Shi

Abstract

This article presents a wideband, low-jitter fre- quency synthesizer utilizing a dual-mode voltage-controlled oscil- lator (VCO). Mode imbalance in the dual-mode VCO is analyzed theoretically and compensated through the proposed symmet- ric figure-8 transformer and capacitor arrays. The compact mode-switching circuitry fundamentally eliminates mode ambi- guity in multi-mode autonomous circuits. A computer-aided algo- rithm based on sequential least-squares programming (SLSQP) and hierarchical optimization method is developed to automat- ically optimize the capacitor array in the wideband VCO. The implemented dual-mode VCO suppresses the phase noise (PN) difference across the operating frequency range, which further enables a sub-sampling phase-locked loop (SSPLL) to achieve near-minimum jitter across a wide frequency range without loop gain adaptation. Fabricated in a 40-nm CMOS process, the wide- band SSPLL covers the frequency range of 7.9–14.3 GHz with 14.1–17.2-mW power consumption and occupies only 0.18-mm 2 area. The SSPLL achieves better than −115-dBc/Hz in-band PN at a 10-GHz carrier. The rms jitter is less than 85 fs across the whole frequency range. The corresponding figure-of-merit tuning (FoMT ) is −247.1 to −248.1 dB.