JSSC 2023第9期Data Converters55nm CMOSNeural Network Accelerator

A 1 V 107 µW 15-Bit Pseudo-Pseudo-Differential Incremental Zoom ADC Zhaonan Lu H

一种1V供电、107µW功耗的15位伪伪差分增量缩放ADC

89.9dB SNR/0.378ms转换时间/1.07µW@1V

模数转换器增量型ADC伪差分结构低功耗设计CMRR增强

▸创新点1：采用伪伪差分(PPD)结构，通过两个单端3位SAR ADC和一个单端三阶增量型ADC处理差分输入信号，有效提高共模抑制比(CMRR)，同时降低功耗和面积开销。

▸创新点2：引入三相位时钟技术，消除正负输入信号采样之间的半周期延迟，显著提升ADC的CMRR性能，优化了差分信号处理的同步性。

▸创新点3：混合SAR与增量型ADC架构，结合SAR ADC的高速度和增量型ADC的高精度，在1V电源下实现107µW超低功耗和89.9dB SNR的高性能指标。

▸创新点4：采用55nm CMOS工艺实现，在0.378ms转换时间内达到180.8dB Schreier FoM，展示了该设计在低功耗高精度ADC领域的卓越性能。

Abstract

This article presents a 15-bit pseudo-pseudo- differential (PPD) incremental zoom analog-to-digital converter (ADC). It employs two single-ended (SE) 3-bit successive- approximation-register (SAR) ADC and a third-order SE incre- mental 16 ADC to process a pair of differential input signals. A novel three-phase clock helps eliminate the half-cycle delay between the positive and the negative input sampling, boosting this work’s common-mode-rejection ratio (CMRR). Fabricated in 55 nm CMOS technolog