← 返回 JSSC 论文列表JSSC 2023第9期Data Converters180nm CMOSDelta-Sigma ADC
A 372 µW 10 kHz-BW 1092 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Co
提出一种嵌套式Delta-Sigma调制器结构,通过混合模拟数字设计实现高能效和低失真。
372 µW, 10 kHz带宽, 109.2 dB SNDR, 183.5 dB FoM S
嵌套Delta-Sigma调制器混合模拟数字设计滞回比较量化高能效低失真
▸嵌套式Delta-Sigma调制器结构(内嵌模拟DSM与外混合DSM)
▸采用滞回比较MSB-pass量化器
▸数字友好设计,灵活性强
Abstract
This article presents a nested delta-sigma modulator
(DSM) structure, where an inner analog DSM is embedded in an
outer analog-digital-hybrid DSM. The outer hybrid DSM is com-
posed of the inner analog DSM, a digital filter, and a hysteresis-
comparison MSB-pass quantizer. The internal signal swing of the
inner analog DSM can be significantly suppressed by the outer
DSM loop, thus achieving good power efficiency. Compared to
conventional system-level signal swing optimization techniques,
the pro