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JSSC 2023第9期Data Converters180nm CMOSDelta-Sigma ADC

A 372 µW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization Yuekang Guo

提出一种嵌套式Delta-Sigma调制器结构,通过混合模拟数字设计实现高能效和低失真。
372 µW, 10 kHz带宽, 109.2 dB SNDR, 183.5 dB FoM S
嵌套Delta-Sigma调制器混合模拟数字设计滞回比较量化高能效低失真
嵌套式Delta-Sigma调制器结构(内嵌模拟DSM与外混合DSM)
采用滞回比较MSB-pass量化器
数字友好设计,灵活性强
Abstract
This article presents a nested delta-sigma modulator (DSM) structure, where an inner analog DSM is embedded in an outer analog-digital-hybrid DSM. The outer hybrid DSM is com- posed of the inner analog DSM, a digital filter, and a hysteresis- comparison MSB-pass quantizer. The internal signal swing of the inner analog DSM can be significantly suppressed by the outer DSM loop, thus achieving good power efficiency. Compared to conventional system-level signal swing optimization techniques, the proposed nested DSM does not suffer from residual signal error issues and distortion leakage and is more digital-friendly with great flexibility. Fabricated in a 180 nm CMOS, the proto- type analog-to-digital converter (ADC), using the nested DSM structure with hysteresis-comparison MSB-pass quantization, achieves signal-to-noise ratio (SNR)/signal-to-noise-and-distortion ratio (SNDR)/spurious-free dynamic range (SFDR)/dynamic range (DR) of 110 dB/109.2 dB/119.6 dBc/110.3 dB, respectively. It achieves a measured Schreier figure of merit (FoM S) of 183.5 dB, which is among the best FoM S of the state-of-the-arts.