JSSC 2023第9期Data Converters65nmSAR ADC

A 4-Bit Mixed-Signal MAC Macro With One-Shot ADC Conversion

提出一种用于DNN加速器的4位混合信号MAC宏，仅需一次ADC转换完成512次4×4位MAC运算。

65nm CMOS, 56.3 GOPS, 345.3µW, 164 TOPS/W

混合信号MAC电荷域计算SAR ADC神经网络加速器能效优化

▸创新点1：电荷域单次ADC转换技术（电路创新）。通过在SAR ADC中采样部分MAC乘积到适当大小的电容器上，实现512个4×4位MAC操作仅需1次ADC转换，显著降低能耗。

▸创新点2：基于旁路窗口的转换跳过节能机制（系统创新）。SAR ADC采用旁路窗口技术，跳过不必要的转换步骤，进一步减少能量消耗，提升整体能效。

▸创新点3：嵌入式ReLU激活功能（电路创新）。在SAR ADC中集成ReLU激活功能，减少额外电路开销，简化系统设计，同时提高处理效率。

▸创新点4：高能效设计（系统创新）。在65-nm CMOS工艺下实现164 TOPS/W的能效，通过优化电荷域操作和ADC设计，显著提升DNN加速器的性能。

Abstract

This work proposes a charge-domain 4-bit multiply- and-accumulate (MAC) macro for deep neural network (DNN) accelerators. The proposed macro requires only 1 analog to digital converter (ADC) operation for the entire 512 4 × 4 b MAC. The one-shot conversion is achieved by sampling partial MAC products onto properly sized capacitors in the SAR ADC. As a result, all MAC operations are finished in the charge domain by the end of ADC sampling, allowing only 1 analog-to-digital (A/D) conversion per multi-bit MAC. To further reduce energy consumption, the SAR ADC features bypass window-based conversion skipping and embedded rectified linear unit (ReLU) activation. The prototype is fabricated in 65-nm complementary metal-oxide semiconductor (CMOS) process with an active area of 0.18 mm 2. The measured throughput is 56.3 giga operations per second (GOPS) with 345.3 µW power consumption, achiev- ing 164 tera operations per watt (TOPS/W) energy efficiency.