JSSC 2023第9期Data Converters7nmPLL

A Calibration-Free Fractional- N Analog PLL With Negligible DSM Quantization Noi

提出一种无需校准的分数N模拟PLL，通过过采样DSM显著降低量化噪声。

4.884 GHz, 154-fs rms jitter, FOM 255.8 dB

分数N锁相环量化噪声过采样多路径相位检测线性RDAC

▸创新点1：过采样DSM技术通过提高调制器时钟频率显著降低量化噪声，无需额外校准，实现了154-fs rms抖动的高精度性能（系统创新）

▸创新点2：多路径相位检测器设计解决了传统PLL中DSM过采样带来的时序冲突问题，支持高频操作且功耗优化（电路创新）

▸创新点3：线性RDAC重组技术将电阻DAC的非线性误差转化为共模噪声，通过差分结构抑制，提升相位噪声性能（方法创新）

▸创新点4：整体架构在7nm工艺下实现4.884GHz工作频率，FOM达255.8dB，兼顾高频与低功耗（系统级性能创新）

Abstract

An analog fractional- N phase-locked loop (PLL) is presented, which largely eliminates quantization noise by overclocking the delta–sigma modulator (DSM). The overclocking technique, enabled by a multipath phase detector and lin- ear resistor-DAC (RDAC) recombination, does not require a high-reference frequency and does not require calibration. A low- power 7-nm prototype operating at 4.884 GHz exhibits 154-fs rms jitter and a figure of merit (FOM) of 255.8 dB.