← 返回 JSSC 论文列表JSSC 2023第10期RF & WirelessVCOEqualizer
A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter
提出一种高效能接收器，采用双反馈嵌套环CDR技术，提升高频抖动容限。
103 fJ/b/dB at 26 Gb/s
高效能接收器时钟数据恢复相位旋转器抖动容限均衡方案
▸创新点1：双反馈嵌套环时钟数据恢复电路(DF-CDR) - 该方法创新通过结合直接调制路径和基于相位旋转器的反馈机制，显著提高了高频抖动容忍度（提升0.15 UI），同时优化了时钟恢复的稳定性和响应速度。
▸创新点2：基于VCO和PI的相位旋转器 - 这一电路创新在锁相环(PLL)内部实现了电压控制振荡器(VCO)和相位插值器(PI)的高效协同，通过动态相位调整提升了信号处理的精度和能效比。
▸创新点3：边缘优先均衡方案 - 该系统创新通过优化决策反馈均衡器的时序控制，降低了功耗和硬件复杂度，同时支持连续时间线性均衡器的自适应调整和接收器前端的背景偏移校准。
▸创新点4：三阶段锁存比较器 - 这一电路创新采用多级锁存结构，实现了高速直接反馈均衡器的设计，显著提升了数据传输速率（达到26 Gb/s）和能效比（103 fJ/b/dB）。
Abstract
A 10–26 Gb/s energy-efficient receiver incorpo- rating a dual-feedback nested loop clock and data recov- ery circuit (DF-CDR) is proposed. Combining a direct modulation path on voltage-controlled oscillator (VCO) and phase interpolator (PI)-based phase rotator inside a phase locked loop (PLL), it improves high-frequency jitter tolerance by 0.15 UI. An edge-first equalization scheme is proposed to reduce power and hardware overhead of decision feedback equalizers. Meanwhile, it facilitates adaptive equalization of continuous time linear equalizer, and background offset calibration of the receiver frontend. A three-stage latch comparator is adopted to enable high-speed direct feedback equalizer. By applying PRBS-31 test pattern through a 32 dB loss channel, the receiver is error-free and features the best energy efficiency of 103 fJ/b/dB at 26 Gb/s.