A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating

Abstract

This work presents a 14-bit 500 MS/s single-channel pipelined-successive-approximation-register (SAR) analog-to- digital converter (ADC) with an adaptively biased floating inverter amplifier (AB-FIA) as the residue amplifier (RA) and a hybrid reference ripple mitigation (H-RRM) technique to relax the power and area burden on the reference stabilization. Lever- aging the adaptively biased architecture in the last stage FIA, the speed and open-loop gain of the proposed two-stage FIA are enhanced compared with the conventional cascode counterpart. Besides, the impact of the reference error on the pipelined-SAR conversion accuracy is alleviated by hybridizing the improved reference ripple cancellation (RRC), reference ripple neutraliza- tion (RRN), and reference buffer (RBUF). The improved RRC removes the potential noise coupled from the floating capacitor to counter the decision error during the sub-SAR conversion in the first stage. Meanwhile, the RRN facilitates a rapid reference recovery. These acts constitute the H-RRM, which assists a high-speed and high-resolution pipelined-SAR process with a relaxed integrated reference RBUF with low-power and compact area. The prototype ADC was fabricated in a 28 nm CMOS process; it consumes 6.34 mW total power at 500 MS/s, including 2.4 mW dynamic power of RBUF. It occupies an active area of 0.018 mm2, which the ADC core area of 0.0168 mm 2 and the area of RBUF with a 2.3 pF decoupling capacitor is 0.00105 mm 2. The measured signal to n