JSSC 2023第10期Data Converters28nmSAR ADC

A 14b 500 MSs Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation

一款采用自适应偏置浮动逆变放大器（AB-FIA）和混合参考纹波抑制技术（H-RRM）的14位500MS/s单通道流水线-SAR ADC。

28nm CMOS, 6.34mW总功耗, 500MS/s, 0.018mm²面积

流水线-SAR ADC自适应偏置参考纹波抑制浮动逆变放大器高速高分辨率

▸自适应偏置浮动逆变放大器（AB-FIA）

▸混合参考纹波抑制技术（H-RRM）

▸改进的参考纹波消除（RRC）和参考纹波中和（RRN）

Abstract

This work presents a 14-bit 500 MS/s single-channel pipelined-successive-approximation-register (SAR) analog-to- digital converter (ADC) with an adaptively biased floating inverter amplifier (AB-FIA) as the residue amplifier (RA) and a hybrid reference ripple mitigation (H-RRM) technique to relax the power and area burden on the reference stabilization. Lever- aging the adaptively biased architecture in the last stage FIA, the speed and open-loop gain of the proposed two-stage FIA are enhanced c