JSSC 2023第10期Data Converters28nmSAR ADC

A 307 mW 30 MHz-BW 732 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self

一种校准自由的双通道时间交织噪声整形SAR ADC，采用二阶误差前馈技术，实现高分辨率和带宽。

28 nm CMOS, 1 V supply, 330 MHz operating frequency, 73.2 dB SNDR over 30 MHz bandwidth, 3.07 mW power consumption

噪声整形SAR ADC时间交织二阶误差前馈动态残差放大器高分辨率

▸校准自由的双通道时间交织噪声整形SAR ADC

▸二阶误差前馈技术增强噪声整形效果

▸动态残差放大器降低偏移并提高转换效率

Abstract

A noise-shaping successive approximation register (NS-SAR) ADC combines the merits of the 1-6 and SAR ADC, transforming it into an emerging ADC architecture to reach high resolution with good power efficiency. The single-channel NS-SAR with high resolution, however, suffers from bandwidth (BW) limitations. The time-interleaved (TI) NS-SAR mitigates the speed bottleneck but faces challenges in obtaining high resolution and BW simultaneously due to the lack of a sharp noise transfer function (NTF)