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JSSC 2023第10期RF & Wireless65nm

A 37–43.5-GHz Phase and Amplitude Detection Circuit With 0.049 ◦ and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD

一种用于5G相控阵校准的高精度相位和幅度检测电路,采用39 GHz–150 kHz下变频方案。
65nm CMOS, 1V, 50mW, 1.43mm², 37-43.5GHz, <0.049°和0.036-dB RMS误差
5G相控阵相位检测幅度检测注入锁定分频器CMOS
采用39 GHz–150 kHz下变频方案分离检测相位和幅度信息
使用基于变压器的注入增强技术实现宽带参考信号生成
实现16.3–23.4 GHz宽锁定范围的注入锁定分频器
Abstract
This article introduces a high-accuracy phase and amplitude detection circuit for 5G phased-array cali- bration. By utilizing a 39 GHz–150 kHz down-conversion scheme, the phase and amplitude information are detected separately with a phase-to-digital converter (PDC) and an analog- to-digital converter (ADC). In addition, to reduce the number of reference signals, a divide-by-4 injection-locked frequency divider (ILFD) using a transformer-based injection-enhancing technique is implemented for wideband reference signal genera- tion. This ILFD realizes a wide locking range of 16.3–23.4 GHz (35.8%) with 5.05-mW power consumption. The detection circuit achieves less than 0.049 ◦ and 0.036-dB detection rms errors at 39 GHz. The wideband high-accuracy detection is also achieved from 37 to 43.5 GHz. The total power consumption is 50 mW with a 1-V VDD. The total core area is 1.43 mm 2 in a 65-nm CMOS process.