JSSC 2023第10期Memory40nmNeural Network Accelerator

A Charge Recycling Logic Data Links for Single- and Multiple-Channel IOs Han Wu

提出一种新型电荷回收逻辑，用于单通道和多通道IO，显著降低功耗。

40nm CMOS, 2.56 Gb/s (TSV), 5.12 Gb/s (T-Line), 32.2%-47% 能效提升

电荷回收IO接口功耗优化TSV传输线

▸电荷回收逻辑实现>20%的功耗降低

▸适用于TSV和传输线链路的通用CR技术

▸多通道CR在相反转换期间补充电荷

Abstract

Wide input-output (IO) chip-to-chip interfaces, such as 3-D chip stacking [through-silicon via (TSV)], silicon inter- poser in high-bandwidth memory (HBM), and other 2.5-D chip-to-chip interface, handle a large amount of data in the server and artificial intelligence (AI) applications. With a large number of IOs, power consumption becomes a huge burden. This article presents a novel charge recycling (CR) logic with >20% power reduction under random data streaming. The presented generic CR techni