← 返回 JSSC 论文列表JSSC 2023第10期Analog Circuits65nm
A Process-Scalable Ultra-Low-V oltage Sleep Timer With a Time-Domain Amplifier a
提出一种采用时间域放大器的超低电压睡眠定时器，实现高精度温度校准和低功耗。
65nm CMOS, 0.4V, 63nW, 180kHz, 2.73ppm/°C
睡眠定时器超低电压时间域放大器频率锁定环温度校准
▸创新点1：超低电压频率锁定环架构（FLL）通过优化设计在0.4V超低电压下工作，显著降低功耗至63nW，同时保持180kHz输出频率，解决了传统架构在工艺缩放下的泄漏电流激增问题（方法创新）
▸创新点2：时间域放大器（TDA）利用时间信号而非电压信号进行放大，避免了模拟电路在超低电压下的精度损失，提升温度依赖性至2.73ppm/°C（电路创新）
▸创新点3：无开关电阻倍增器（SLRM）结合栅极泄漏利用技术，通过被动元件替代主动开关，减少动态功耗并增强工艺可扩展性（电路创新）
▸创新点4：基于查找表（LUT）和温度传感器（TS）的校准系统，实现高精度温度补偿，将传统RC定时器的温度依赖性提升一个数量级（系统创新）
Abstract
The on-chip sleep timer is a compact and
cost-effective solution that provides high-precision temperature
accuracy through the use of a lookup table (LUT) and dedicated
temperature sensor (TS). However, maintaining energy efficiency
while integrating an accurate sleep timer is challenging due to
the significant increase in leakage currents with process scaling
and temperature. The proposed sleep timer overcomes these
limitations by utilizing an ultra-low-voltage (ULV) frequency-
locked-loop (FLL