← 返回 JSSC 论文列表JSSC 2023第10期Clocking & PLLs65nmNeural Network Accelerator
A Serrodyne Modulator-Based Fractional Frequency Synthesis Technique for Low-Noi
提出一种基于锯齿波调制器的低噪声分数频率合成技术。
65nm CMOS, 5GHz输入, 2.4899GHz输出, DJ PP降低≥7.2×
锯齿波调制器分数频率合成低噪声确定性抖动动态CMOS
▸锯齿波调制器降低确定性抖动
▸动态CMOS正交分频器实现低功耗低抖动
▸适用于多输出时钟生成和快速频率切换
Abstract
A serrodyne modulator (SM)-based fractional fre-
quency synthesizer is presented. The SM receives its input signal
with large deterministic jitter (DJ) from a multiplexer (MUX)-
based fractional divider, and by employing linear sawtooth
modulation of delay, attenuates the DJ, achieving low-noise
fractional frequency synthesis. With a small footprint (0.01 mm 2
in 65-nm CMOS), it is ideal for multi-output clock generation,
fast frequency switching, and spread-spectrum clocking (SSC).
With an on-c