A Serrodyne Modulator-Based Fractional Frequency Synthesis Technique for Low-Noise, GHz-Rate Clocking Ahmad Sharkia , Student Member , IEEE

Abstract

A serrodyne modulator (SM)-based fractional fre- quency synthesizer is presented. The SM receives its input signal with large deterministic jitter (DJ) from a multiplexer (MUX)- based fractional divider, and by employing linear sawtooth modulation of delay, attenuates the DJ, achieving low-noise fractional frequency synthesis. With a small footprint (0.01 mm 2 in 65-nm CMOS), it is ideal for multi-output clock generation, fast frequency switching, and spread-spectrum clocking (SSC). With an on-chip phase-locked-loop (PLL)-generated 5 GHz signal as input, and a 2.4899 GHz output, the circuit achieves ≥7.2× reduction in the peak-to-peak DJ (DJ PP). With an external 8.7 GHz input, and a 4.33 GHz output, DJ PP reduction is ≥6.2×. We also present a dynamic clocked-CMOS (C 2MOS) quadrature divider to realize a low-power and low-jitter operation.