A Wide-Load-Range and High-Slew Capacitor-Less NMOS LDO With Adaptive-Gain Nested Miller Compensation and Pre-Emphasis

Abstract

This article proposes an output capacitor-less NMOS low-dropout regulator (LDO) using wide-range adaptive- gain nested Miller compensation (W AG-NMC) and pre-emphasis inverse (PI) biasing. Due to W AG-NMC, the LDO can provide a wide range of load current ( ILOAD) from 0.1 to 300 mA while maintaining sufficiently high phase margin (PM) above 60 ◦ at all ILOAD conditions. W AG-NMC also extends a loop bandwidth (BW) up to 17.5 MHz with using only small compensation capacitors (CC) of 6.3 pF in total. Moreover, PI biasing enhances a slew rate (SR) at the gate of the NMOS power transistor by injecting an adaptive PI current into a supersource follower (SSF), which further improves transient response. The proposed LDO fabricated in a 180-nm CMOS process was fully integrated with an on-chip load capacitor ( CL) of 100 pF. The LDO ensures small undershoot and overshoot of 48 and 59 mV , respectively, against large 1ILOAD of 299 mA due to wide-BW and high SR. The proposed LDO also achieves a best figure of merit (FoM) of 1.72 ps among the state of the arts.