An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET

Abstract

Bayesian neural networks (BNNs) have been proposed to address the problems of overfitting and overconfident decision making, common in conventional neural networks (NNs), due to their ability to model and express uncertainty in their pre- dictions. However, BNNs require multiple inference passes to pro- duce the necessary posterior distributions used to generate these highly desirable uncertainty estimates. As such, BNNs require not only an efficient, high-performance multiply-accumulation (MAC) operation but also an efficient Gaussian random number generator (GRNG) with high-quality statistics. In this article, an NN accelerator chip, leveraging a multi-bit analog compute- in-memory (CiM) static random-access memory (SRAM) macro, with a tightly coupled and highly efficient GRNG scheme, is pre- sented in the Intel 22FFL process. The CiM macro achieves a peak energy efficiency of 32.2 TOP/sW, with 8-bit precision, while ensuring accurate on-chip matrix-vector multiplications (MVMs) with a computation error less than 0.5%. The variable precision GRNG achieves a peak throughput of 7.31 GSamp/s for an energy efficiency of ∼1 TSamp/J. Overall, our proposed system achieves a peak energy efficiency of 1170 GOP/s/W, a 35–133× improvement over the state-of-the-art BNN accelerators, with 98.14% accuracy for the MNIST dataset.