JSSC 2023第10期Digital CircuitsNeural Network Accelerator

SNPU An Energy-Efficient Spike Domain Deep- Neural-Network Processor With Two-St

提出一种高效能脉冲域深度神经网络处理器SNPU，采用两步编码和全稀疏处理单元提升能效。

输入脉冲编码功耗降低99.4%，操作减少43.5%与71.8%

脉冲神经网络能效优化稀疏处理两步编码计算复用

▸创新点1：两步编码（神经编码与计算编码）——方法创新。通过神经编码消除伪随机数生成器（PRNGs），减少冗余内存访问，同时计算编码采用多级编码和脉冲序列分解，显著减少操作次数，提升能效。

▸创新点2：全稀疏处理单元——系统创新。设计了一种能够处理各种稀疏条件的单元，解决了现有处理器在特定稀疏条件下性能受限的问题，提升了处理器的通用性和效率。

▸创新点3：脉冲序列分解减少计算操作——方法创新。通过计算重用减少脉冲序列的累加操作，相比传统脉冲神经网络处理减少了71.8%的操作，大幅降低了计算复杂度。

▸创新点4：神经元链接与脉冲序列分配器——电路创新。支持可变时间窗口大小，提高了处理单元（PE）的利用率，使SNPU的PE利用率提升了23.1%，进一步优化了系统性能。

Abstract

In this article, an energy-efficient spike domain deep-neural-network processor (SNPU) is proposed. Recently, many sparsity-aware processors were proposed to increase energy efficiency. However, because the activation of the real-world network was not high compared to the ideal condition, they were unable to completely employ integrated zero skipping logic. In addition, they employed weight sparsity by pruning, but their zero skipping logic was designed to perform best only under specific sparsi