SNPU: An Energy-Efficient Spike Domain Deep- Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit

Abstract

In this article, an energy-efficient spike domain deep-neural-network processor (SNPU) is proposed. Recently, many sparsity-aware processors were proposed to increase energy efficiency. However, because the activation of the real-world network was not high compared to the ideal condition, they were unable to completely employ integrated zero skipping logic. In addition, they employed weight sparsity by pruning, but their zero skipping logic was designed to perform best only under specific sparsity condition. We adopt two-step encoding (neural and computing encoding) and an omni-sparsity handling unit to solve these issues. The input neural encoding eliminates pseudo-random number generators (PRNGs) for the previous encoding, and the output neural encoding reduces redundant memory access. As a result, weight can be reused by a delayed factor, while input spike encoding consumes 99.4% less power compared to the Poisson encoder. Also, SNPU uses computing encoding with multi-level encoding and spiketrain decomposition. The multi-level encoding reduces the time-window size by merg- ing several spikes, and SNPU uses a single shift-and-accumulation (SAC) rather than several accumulations, reducing 43.5% of operations compared to single-level encoding. In addition, the spike-train decomposition is proposed to decrease the number of SACs by computation reuse, resulting in a reduction of 71.8% operations compared to previous spiking neural-network (SNN) processing, which cannot reuse c