A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links Jaeyoung Seo , Sooeun Lee

Abstract

This article presents a 20-Gb/s/pin 0.0024-mm 2 single-ended data-embedded clock signaling (DECS) transceiver (TRX) for short-reach on-chip links. The receiver (RX) directly recovers (self-slicing) and deserializes (auto-deserialization) the data from the DECS input of the RX front-end without a clock and data recovery (CDR) or clock and data alignment (CDA) circuits, while improving the timing requirement and the toler- ance to duty cycle error and supply noise. At 20 Gb/s/pin, the horizontal eye was measured 0.99 UI at nominal and remained equal to or larger than 0.88 UI either when the clock duty cycle changed from 40% to 60% or when a 50-MHz 300-mV p−p sinusoidal supply noise was injected to the RX from a printed circuit board (PCB). In addition, the proposed RX could tolerate a 200-MHz 300-mV p−p sinusoidal supply noise and 200-mV p−p crest factor 7 (CF7) Gaussian supply noise, while achieving 0.90 UI horizontal eye size in both cases. Because complex clocking circuits were removed, the active RX core excluding on- die-terminations (ODTs) achieved the smallest area occupancy of 0.000058 mm 2 and decent energy efficiency of 0.18 pJ/b. With the proposed technique, a compact high-speed short-reach on- chip link is feasible without expensive high-speed duty cycle correction (DCC), duty cycle detection (DCD), CDR, or CDA. The proposed TRX was fabricated in 28-nm CMOS low-power performance (LPP) technology. Manuscript received 28 June 2022; revised 25 November 2022 and 16 Marc