← 返回 JSSC 论文列表JSSC 2023第11期RF & Wireless28nmNeural Network Accelerator
A 20-GbsPin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Fron
一种20Gb/s/pin的单端DECS收发器，无需CDR或CDA电路，具有高时序容忍度和抗电源噪声能力。
20Gb/s/pin, 0.0024-mm², 0.18 pJ/b, 0.99 UI水平眼图
单端DECS收发器无CDR高时序容忍度抗电源噪声28nm CMOS
▸无需时钟和数据恢复（CDR）或时钟和数据对齐（CDA）电路
▸提高时序要求和容忍时钟占空比误差及电源噪声
▸实现紧凑面积（0.000058 mm²）和高能效（0.18 pJ/b）
Abstract
This article presents a 20-Gb/s/pin 0.0024-mm 2
single-ended data-embedded clock signaling (DECS) transceiver
(TRX) for short-reach on-chip links. The receiver (RX) directly
recovers (self-slicing) and deserializes (auto-deserialization) the
data from the DECS input of the RX front-end without a clock
and data recovery (CDR) or clock and data alignment (CDA)
circuits, while improving the timing requirement and the toler-
ance to duty cycle error and supply noise. At 20 Gb/s/pin, the
horizontal e