An Energy-Efficient Design of TSV IO for HBM With a Data Rate up to 10 Gbs Ji-Yo

Abstract

In this study, a low-power through-silicon via (TSV) I/O employing a low supply voltage (VDDL) for low-power oper- ation with a 65-nm complementary metal–oxide–semiconductor (CMOS) process is proposed for high-bandwidth memory (HBM). The proposed TSV I/O satisfies the following requirements for implementing HBM I/O: a sufficient voltage margin of the transmitted signal, no static power consumption, and a small area overhead. For the improvement of the signal integrity (SI) under (VDDL) operation