An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing

Abstract

As neural-recording devices get denser and generate more data due to ever higher channel counts, on-chip and online neural signal processor (NSP) becomes crucial to reduce the data-transmission power and to enable real-time closed-loop applications with minimum latency. For this purpose, we report an online spike-sorting integrated circuit (IC) able to process neural signals from 384 channels with software-comparable accuracy. By combining three main innovations, our design drastically improves the fundamental trade-off between hardware resources and real-time performance. Specifically, a central spike detection (CSD) algorithm is designed to mitigate the impact of redundant spikes on accuracy. Second, a peak first and second derivative extrema (FSDE) method is devised to accomplish robust feature extraction (FE) across various datasets. Finally, to deal with the trade-off between accuracy and complexity in the clustering stage, a geometry-aware OSort (Geo-OSort) algorithm is developed. A prototype chip has been fabricated in a 22 nm FDSOI CMOS process. The measurement results show that the designed NSP achieves an area of 0.0013 mm 2/channel, a power consumption of 1.78 µW/channel, a latency of 33.9 µs, and an accuracy of 97.7% without clustering pretraining.