JSSC 2023第12期Data Converters28nmSAR ADC

A 10-mW 10-ENoB 1-GSs Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Sw

提出一种基于环形放大器的低功耗12位1GS/s混合架构ADC。

28nm CMOS, 62.5dB SNDR, 10.6mW, 169.2dB FoM S

环形放大器混合架构ADC时间交织低功耗参考缓冲

▸采用环形放大器降低残差放大功耗

▸分裂MDAC提高环形放大器性能

▸开关参考解耦电容技术提升PSRR

Abstract

This article presents a 12-bit 1-GS/s ring-amp-based analog-to-digital converter (ADC) with a pipelined and time- interleaved successive approximation register (TI-SAR) hybrid architecture. This architecture utilizes backend time-interleaving for power and design complexity reduction while eliminating the sampling time skew. A ring amplifier (ring-amp) is used in this architecture to significantly reduce the power of residue amplification by about ten times over a prior work. A high-speed PVT-ro