A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET

Abstract

This work presents a D-band (110–170 GHz) receiver (RX) with integrated analog-to-digital converter (ADC) and phase-locked loop (PLL). The receiver front end (RXFE) con- sists of a coupled-line-based Guanella balun matching network, 140-GHz low-noise amplifier (LNA), and Cherry–Hooper (CH) amplifier providing >20-GHz baseband bandwidth. A quadra- ture PLL provides I/Q local oscillator (LO) signals for down-conversion. Two 32-GS/s hybrid voltage- and time-domain ADCs digitize the RXFE output. The fully integrated 22-nm FinFET CMOS prototype achieves a peak data rate of 128 Gb/s using 16-QAM modulation with −15.2-dB EVM and consumes 246 mW for 1.95-pJ/b efficiency. The stand-alone RXFE without ADC provides 160-Gb/s data rates with −16.4-dB EVM and consumes 166 mW for 1.04-pJ/b efficiency.