← 返回 JSSC 论文列表JSSC 2023第12期RF & Wireless22nmPLLLNA
A 128-Gbs D-Band Receiver With Integrated PLL and ADC Achieving 195-pJb Efficien
一款集成PLL和ADC的D波段接收器，实现128Gb/s数据速率和1.95pJ/b能效。
22nm FinFET CMOS, 128Gb/s, 16-QAM, -15.2dB EVM, 246mW, 1.95pJ/b
D波段接收器相位锁定环模数转换器低噪声放大器能效
▸集成PLL和ADC的D波段接收器
▸采用耦合线Guanella巴伦匹配网络
▸混合电压和时间域ADC设计
Abstract
This work presents a D-band (110–170 GHz)
receiver (RX) with integrated analog-to-digital converter (ADC)
and phase-locked loop (PLL). The receiver front end (RXFE) con-
sists of a coupled-line-based Guanella balun matching network,
140-GHz low-noise amplifier (LNA), and Cherry–Hooper (CH)
amplifier providing >20-GHz baseband bandwidth. A quadra-
ture PLL provides I/Q local oscillator (LO) signals for
down-conversion. Two 32-GS/s hybrid voltage- and time-domain
ADCs digitize the RXFE output. The