JSSC 2023第12期Power Management28nmPLL

A Low-Spur and Low-Jitter Fractional- N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering Simone M. Dartizio , Member , IEEE

提出一种基于逆常数斜率DTC的低杂散低抖动分数N数字PLL。

28nm CMOS, 0.33 mm2, 17.2 mW, -70 dBc, 77 fs

分数N数字PLL低杂散低抖动DTC线性度量化误差随机化

▸创新点1：逆常数斜率DTC提高线性度（电路创新）。通过设计逆常数斜率DTC，有效抑制了沟道长度调制和非线性寄生电容的影响，显著提升了DTC的线性度，从而降低了分数杂散。

▸创新点2：FCW减法抖动技术随机化量化误差（方法创新）。采用FCW减法抖动技术，随机化了驱动PLL分频比的16调制器的量化误差，无需增加DTC动态范围，将分数杂散推至PLL带宽之外。

▸创新点3：无需增加DTC动态范围（系统创新）。通过优化设计，在不增加DTC动态范围的情况下，实现了低杂散和低抖动的性能，降低了系统复杂度和功耗。

▸创新点4：高性能指标（性能创新）。在9.25 GHz附近的分数-N通道中，测得带内分数杂散低于-70 dBc，均方根抖动为77 fs，实现了-249.9 dB的抖动功率品质因数。

Abstract

This work presents a low-spur and low-jitter fractional-N digital phase-locked loop (PLL). To reduce the fractional spurs caused by the non-linearity of the digital-to-time converter (DTC), two novel solutions are introduced. First, the inverse-constant-slope DTC achieves high-linearity, thanks to its immunity to channel-length modulation and non-linear parasitic capacitances. Second, the frequency-control-word (FCW) sub- tractive dithering technique randomizes the quantization error of the 16 modulator driving the PLL divider ratio without requiring an increased DTC dynamic range and pushing the fractional spurs outside the PLL bandwidth. The prototype, implemented in a 28-nm CMOS process, has an active area of 0.33 mm2 and dissipates 17.2 mW. At fractional- N channels near 9.25 GHz, the measured in-band fractional spurs and the rms jitter are below −70 dBc and 77 fs, respectively, leading to a jitter-power figure of merit of −249.9 dB.