← 返回 JSSC 论文列表JSSC 2023第12期RF & Wireless65nmPLLDRAM
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution
一种基于单LC-VCO的5G FR1宽带LO生成器,采用子采样架构和数字校准技术实现低相位噪声。
65nm CMOS, 超低抖动, 覆盖5G FR1全频段
5G FR1LO生成器LC-VCO子采样PLL相位噪声
▸使用相位旋转分频器(PRD)降低PLL频率调谐范围至21%
▸采用个体延迟单元可控数字环路滤波器(IDC-DLF)校准失配并保证精确正交关系
▸结合子采样架构、DAC量化误差消除和数字预失真技术实现超低相位噪声
Abstract
In this work, an ultra-low -jitter wideband cascaded local oscillation (LO) generator for 5G frequency range 1 (FR1) is presented. Using the phase-rotating divider (PRD) of the 2nd-stage ring-oscillator-based frequency multiplier (RO-FM) that can generate fractional multiplication factors ( Ms), the required frequency-tuning range (FTR) of the 1st-stage phase- locked loop (PLL) dramatically decreased to 21%, which can be covered easily by a single low-phase-noise LC-voltage-controlled oscillator (VCO). Thus, the proposed LO generator can cover entire FR1 bands using only one LC tank. To suppress the fractional spurs caused by the mismatches of the delay cells of an RO, an individual-delay-cell-controllable digital loop filter (IDC-DLF) was used to calibrate the mismatches. Since the IDC- DLF equalizes the intervals between the quadrature signals of the RO, it can also naturally guarantee a precise quadrature relationship without any additional calibration. The 1st-stage PLL was designed based on a subsampling architecture, and it used a digital-to-analog converter (DAC)-based quantization error ( Q-error) cancellation, dual-clock-phase generator, and a third-order curve fitting digital predistortion (TCF-DPD) to achieve ultra-low phase noise. The proposed LO generator was fabricated in a 65-nm CMOS process, and it used the power of Manuscript received 5 May 2023; revised 21 July 2023 and 13 September 2023; accepted 28 September 2023. Date of publication 11 October 2023; date