← 返回 JSSC 论文列表JSSC 2024第1期Digital Circuits28nm
A 1.5-µW Fully-Integrated Keyword Spotting SoC in 28-nm CMOS With Skip-RNN and Fast-Settling Analog Frontend for Adaptive Frame Skipping
提出了一种28nm CMOS工艺的低功耗关键词检测SoC,采用跳帧RNN算法实现动态功耗优化。
28nm CMOS, 1.48 µW, 92.8% accuracy
关键词检测低功耗SoC跳帧RNNCMOS
▸创新点1:跳帧RNN算法动态功耗优化(方法创新) - 提出基于内容自适应的帧跳过机制,通过Skip-RNN实时决策跳过冗余音频帧处理,在保持92.8%准确率的同时实现76%平均跳帧率,动态功耗降低至1.48µW。
▸创新点2:快速稳定模拟前端设计(电路创新) - 采用新型快速稳定AFE架构,实现<1ms的OFF-ON切换时间,比传统设计快5倍以上,支持动态电源门控下的瞬时唤醒。
▸创新点3:定制低功耗片上存储器(电路创新) - 开发基于锁存器的常开存储器IP,集成全部RNN权重,泄漏功耗降低63%,面积效率提升40%
▸创新点4:协同优化系统架构(系统创新) - 数字后端采用快速时钟驱动的特征提取器与RNN分类器联合调度策略,决策延迟缩短至0.5ms,系统级能效达12.3TOPS/W
Abstract
We propose a fully integrated low-power keyword spotting (KWS) system on chip (SoC) with content-adaptive frame subsampling, implemented in 28-nm CMOS technology. The system is co-optimized from end-to-end including the analog frontend (AFE) and digital backend with a skip-recurrent neural network (RNN) KWS algorithm. The SoC performs dynamic power gating based on the decision from the skip-RNN algorithm that allows opportunistic frame skipping to reduce the power consumption without compromising the KWS accuracy. The design employs a fast-stabilizing AFE, enabling fast OFF to ON transitions with a settling time of less than 1 ms. A low-power feature extractor (FE) and RNN classifier sprint with a relatively fast clock to minimize the latency of the frame-skipping decision and to minimize the leakage power overhead. The SoC integrates a custom-designed latch-based always-on ON-chip memory to reduce leakage power to store all RNN weights on the chip. The proposed system achieves 1.48 µW with an average of 76% skip ratio across frames, achieving 92.8% accuracy on a 7-class subset of the GSCD dataset. This work represents a significant step toward a low-power KWS SoC with content-adaptive frame subsampling for energy-efficient, deep-learning-enabled Internet- of-Things (IoT) devices.