A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ

Abstract

This article presents a high-speed all-digital third- generation high-bandwidth memory (HBM3) interface that achieves reliable memory access at a rate of 9.0 Gb/s/pin at 0.66 and 0.30 V supply voltages. To enhance the access reliability, the interface uses resistor-tuned offset calibration and in situ margin detection techniques; furthermore, a supply noise adapta- tion algorithm, coupled with a high-accuracy digital delay sensor, significantly enhances voltage stability and mitigates the degra- dation of the valid window margin (VWM) under supply voltage variations. Additionally, the use of stacked-I/O and folded-PHY concepts in the HBM3 interface results in an optimal area, enabling seamless alignment with the HBM3 channel structure and effectively minimizing the length of the channels. To demon- strate the effectiveness of the suggested interface, a HBM3 system was implemented with a 4-nm fin field-effect transistor (Fin- FET) technology. This implementation showcases the outstanding energy efficiency of the HBM3 interface, 0.29 pJ/bit, with an improved supply of noise-tolerance while occupying a small area. This work highlights the promising potential of the proposed all- digital HBM3 interface for enabling high-speed memory access in high-performance computing (HPC)/artificial intelligence (AI) computing systems.