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JSSC 2024第1期RF & Wireless4nmPAM-4

A 4-nm 16-Gbspin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter C

4纳米CMOS工艺下16Gbps单端PAM-4收发器，采用切换抖动补偿技术提升时序裕度
16-Gb/s/pin, 0.764-pJ/b
PAM-4CMOS收发器抖动补偿前馈均衡
▸创新点1：切换抖动补偿技术（电路创新）。通过调整前端输出的过渡斜率，显著改善了接收端的时序裕量，从0.31 UI提升至0.37 UI，有效降低了抖动对信号完整性的影响。
▸创新点2：宽松阻抗匹配（系统创新）。采用20 Ω的发射端阻抗替代传统的50 Ω，缓解了PAM-4信号的信噪比退化问题，提升了信号传输的稳定性和效率。
▸创新点3：分数间隔前馈均衡（方法创新）。使用0.8 UI间隔的分数间隔前馈均衡（FS-FFE），进一步优化了眼图开口，相比传统1 UI间隔的FFE设计，眼图开口提升了2.25倍。
▸创新点4：单端PAM-4并行收发器设计（系统创新）。在4 nm CMOS工艺下实现16 Gb/s/pin的单端PAM-4收发器，能效达到0.764 pJ/b，展现了高带宽和低功耗的优异性能。
Abstract
This article presents a 16-Gb/s/pin 0.764-pJ/b single-ended four-level pulse-amplitude modulation (PAM-4) transceiver in a 4-nm CMOS process. A switching-jitter com- pensation technique is proposed in the receiver (RX) to improve timing margins from 0.31 to 0.37 UI at 16 Gb/s, as it adjusts transition slope of the front-end outputs. To compensate for signal-to-noise ratio (SNR) degradation in a PAM-4 signal, relaxed impedance matching is used, where 20  is used as a transmitter (TX) impedance i