A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS

Abstract

This article presents a five-tap delay-line-based feed-forward equalizer (FFE) for 200-Gb/s wireline receiver (RX) in 28-nm CMOS technology. The RX FFE employs ON-chip grounded coplanar waveguides (GCPWs) as delay lines and a one-stage topology for higher bandwidth and lower power. Two large taps are implemented with distributed amplifiers to alle- viate reflection. Cross-connected variable-transconductance cells improve linearity for small coefficients. RC source degeneration in the variable-transconductance cell provides low-frequency equalization that reduces the number of taps. Measurement results indicate that the FFE can equalize the 200-Gb/s data after a 17.2-dB loss channel with an energy efficiency of 0.42 pJ/b. It can also work as a fractional-spaced FFE for the 150-, 100-, and 50-Gb/s data. To the best of our knowledge, this work is the first continuous-time FFE operating at 200 Gb/s.