Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs Agata Iesurum Gra

Abstract

A novel architecture to implement quadrature voltage-controlled oscillators (QVCOs), based on the coupled phase-locked loop (CPLL) technique, is presented. The proposed solution allows to overcome the trade-off between low phase noise and small quadrature error, typical of conventional QVCOs. Both figure-of-merit (FoM) can then be optimized simultaneously. Within the CPLL bandwidth, the QVCO phase noise is even improved by 3 dB with respect to the phase noise of the stan- dalone free-running osc