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DynaPlasia An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator
DynaPlasia是一种基于eDRAM内存计算的可重构空间加速器，通过动态可重构核心架构和新型三模式单元提升能效和面积效率。
28nm CMOS, 20.25mm² die area, 9.6Mb cell capacity, 19.5 TOPS peak throughput, 56.0 TOPS/W peak efficiency
内存计算可重构加速器eDRAM动态可重构能效优化
▸动态可重构核心架构（DRECA）
▸三模式单元（IMC PE、单元DAC、单元单元）
▸分层内存ADC（Hi-ADC）
▸带符号输入带符号权重（SISW）IMC
▸泄漏容忍计算（LTC）
Abstract
This article presents DynaPlasia, a reconfigurable
eDRAM-based in-memory computing (IMC) processor with a
novel triple-mode cell. It enables higher system-level performance
and efficiency in a resource-limited environment. DynaPlasia
proposes five key features that can enhance the energy effi-
ciency and area efficiency of the IMC accelerator: 1) dynamic
reconfigurable core architecture (DRECA), which dynamically
reconfigures the effective IMC macro size according to DNN
workloads; 2) the triple