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A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR
一款60Gbs PAM-4接收器，采用抖动补偿CDR技术，实现低抖动传输与高带宽容忍。
40nm CMOS, 30-60Gb/s, <-8dB JTRAN, 40MHz JTOL带宽, 60%抖动补偿率
PAM-4接收器抖动补偿时钟数据恢复高速通信CMOS
▸创新点1：抖动补偿时钟数据恢复(JCCDR) - 该方法创新通过在CDR中集成抖动补偿电路(JCC)，实现了对输入PAM-4信号抖动的主动补偿，显著降低了抖动传输(JTRAN < -8 dB)，同时保持40MHz宽带宽抖动容忍能力。
▸创新点2：抖动传输衰减技术 - 电路创新体现在JCC的多功能集成，包括抖动检测、互补信号生成和抖动衰减，支持高达60%的抖动补偿比（DC至4MHz），解决了传统CDR在抖动抑制与带宽间的权衡问题。
▸创新点3：宽带宽抖动容忍(40MHz) - 系统创新通过优化环路动态特性，在0.2-UI峰峰值抖动幅度下维持40MHz的JTOL带宽，突破了高速PAM-4接收机对宽带抖动的鲁棒性限制。
▸创新点4：能效优化设计 - 采用40nm CMOS工艺实现12pJ/bit的超低功耗，在30-60Gb/s速率范围内保持无误码运行，展现了系统级能效与性能的协同优化。
Abstract
This article presents a four-level pulse amplitude modulation (PAM-4) receiver (Rx) with a jitter compensation clock and data recovery (JCCDR) for high-speed retimer appli- cation. The JCCDR can attenuate the jitter transfer (JTRAN) from the input PAM-4 signal to the recovered clock and data without sacrificing the jitter tolerance (JTOL) bandwidth. A jitter compensation circuit (JCC) is implemented within the JCCDR to support JTRAN detection, complementary signal generation, and JTRAN attenuation functions. Theoretical analysis is performed to verify the effectiveness and challenges of the proposed method. Prototyped in 40-nm CMOS, the Rx achieves error-free operation with PAM-4 input from 30 to 60 Gb/s. The JCCDR provides an ultralow < −8 dB JTRAN while maintaining a 40-MHz wide JTOL bandwidth with a 0.2-UI PP jitter amplitude. A jitter compensation ratio up to 60% can be supported from dc to 4 MHz.