A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications

Abstract

This article presents a four-phase time-based switched-capacitor low-dropout (SCLDO) regulator that regu- lates an output load voltage ( VOUT) of 0.35–0.95 V with an input voltage ( VIN) of 0.45–1 V . The regulator employs a four-phase time quantizer, which enables high proportional gain control and short transient response time with relatively low quiescent current. In addition, the proposed SCLDO employs a 9.6-pF coupling capacitor ( CC) that is connected to the gate voltage of the pass transistor and VOUT node, thereby reducing the VOUT voltage drop during the load transition. Because the SCLDO utilizes capacitor components when charging and discharging CC, it provides robustness to process and temperature variations even at low- VIN conditions. Therefore, the proposed time-based SCLDO achieved a VOUT settling time of 4.4 ns at VIN = 1 V and 13 ns at VIN = 0.5 V condition. Fabricated in a 28-nm CMOS process, the proposed time-based SCLDO achieves a maximum IOUT of 400 mA and a figure of merit (FoM) of 3.0 fs, with an active area of 0.021 mm 2.