A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-V oltage Multivoltage/ Frequency-Domain Network-on-Chip

Abstract

For a network-on-chip (NoC) with multiple volt- age/frequency domains, metastability hurts the reliability during the clock-domain crossing, especially in the near-threshold- voltage (NTV) region. Conventional multistage synchronizers reduce the probability of metastability but have a high latency penalty. This article presents a technique titled metastability risk prediction and mitigation (MPAM) that predicts the near- future metastability risks by a triple-phase clock monitoring circuitry and mitigates them by a metastability-free clock scheme. Therefore, the MPAM enables only one flip-flop for data synchronization without degrading the reliability against metastability, thus improving the latency and throughput of NoC. We prototyped a 2-by-2 NoC test chip with four independent voltage/frequency domains in a 40-nm low-power (LP) process, featuring the MPAM technique. The measurement shows that the MPAM significantly reduces the metastability condition rate by 10 10 times under different clock frequency ratios. Moreover, by enabling only one flip-flop for synchronization, the MPAM-based NoC achieves packet latency reduction, throughput improvement, and energy efficiency gain by 58%, 13.4%, and 8.6%, respectively.