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JSSC 2024第2期Memory0.18-µmSRAMNeural Network Accelerator

An SRAM-Based Reconfigurable Cognitive Computation Matrix for Sensor Edge Applications Sheng-Yu Peng

提出了一种适用于传感器边缘应用的SRAM可重构认知计算矩阵,支持多象限乘法和多种激活函数。
0.18-µm CMOS, 3.355 TOPS/W
SRAM可重构计算矩阵传感器边缘应用多象限乘法激活函数
支持1、2、4象限乘法
提供ReLU、RBF和Logistic三种激活函数
采用48个失配参数校准提高计算精度
Abstract
A reconfigurable cognitive computation matrix (RCCM) in static random access memory (SRAM) suitable for sensor edge applications is proposed in this article. The proposed RCCM can take multiple analog currents or digital integers as the input vector and perform vector-matrix multiplication with a weight integer matrix. The RCCM can carry out 1-quadrant, 2-quadrant, or 4-quadrant multiplications in the analog domain. Therefore, the digital integers for the inputs or weights stored in the SRAM can be either signed or unsigned, providing extensive usage flexibilities. Furthermore, three commonly used activation functions (AFs), the rectified linear unit (ReLU), radial basis function (RBF), and logistic function are available, convert- ing multiply–accumulation outputs to single-ended currents as the computation results. The resultant output currents can be adopted as the input currents of other RCCMs to facilitate multiple-layer network implementation. A concept-proving pro- totype chip, including a 16 × 16 RCCM with 4-bit input and weight resolutions, is designed and fabricated in a 0.18-µm CMOS process. The computation accuracy that is deteriorated by process variation can be significantly improved by adopting 48 mismatch parameters after calibration. A handwritten digit recognition database, MNIST, is employed to evaluate the chip performance, achieving an average efficiency of 3.355 TOPS/W.