JSSC 2024第2期Data Converters180nmEmerging MemoryNeural Network Accelerator

Design and Implementation of a Hybrid ADCDAC-Free Input-Sparsity-Aware Precision

设计并实现了一种基于180nm CMOS技术的1Mb RRAM存内计算芯片，采用时间分复用电路和稀疏感知技术，免除了DAC和ADC需求。

180nm CMOS, 13.32 Mb/mm2 (22nm节点归一化), 17.36 TOPS/W (INT4)

存内计算RRAM量化感知训练动态可重构稀疏感知

▸时间分复用电路(TDM)免除DAC和ADC

▸稀疏感知输入模块(SAIM)提高计算效率

▸量化感知训练(QAT)和动态可重构移位器(RecSTRs)实现系统可配置性

Abstract

In this work, we design and implement a 1-Mb resistive random access memory (RRAM) processing-in-memory (PIM) chip based on a 180-nm CMOS technology. In this design, a time-division multiplexing (TDM) circuit along with sparsity-aware sense amplifier (SA) and asynchronous counter module (ACM) are proposed to free the chip from digital-to- analog converter (DAC) and analog-to-digital converter (ADC). A sparsity-aware input module (SAIM) is designed to improve computational efficiency for bit-leve