← 返回 JSSC 论文列表JSSC 2024第2期Power Management40nm
Highly Efficient Differential Frequency Doubler With Output Resistance Boosting
采用互补MOS晶体管的V波段高效差分倍频器和D波段四倍频器设计
15.3% CE/3.5dBm输出功率(倍频器),4.7% CE/1.3dBm输出功率(四倍频器)
频率倍增器CMOS转换效率差分电路毫米波
▸利用栅漏寄生电容和栅极串联电感反馈效应提高转换效率
▸通过添加电容缓解NMOS与PMOS晶体管固有失衡
▸采用级联差分倍频器实现四倍频
Abstract
This article presents a differential V-band fre-
quency doubler and a D-band frequency quadrupler that use
complementary MOS transistors. The frequency doubler is
designed to achieve high conversion efficiency (CE) by utilizing
the feedback effect due to the gate–drain parasitic capacitance
and the series inductor at the gate of the transistors. Capacitors
are added to NMOS transistors to alleviate the intrinsic imbal-
ances between NMOS and PMOS transistors. The frequency
quadrupler is composed