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JSSC 2024第2期Other65nmBandgap Reference

Sub-µW Auto-Calibration Bandgap V oltage Reference With 1 σ Inaccuracy of ±0.12% Within −40 ◦C to 120 ◦C Chi-Wa U

提出一种基于电流的带隙电压参考自动校准技术,降低校准成本并提高精度。
22.3 ppm/°C, 1.26 mV/V, ±0.12%
带隙电压参考自动校准温度系数工艺变化数字模拟转换器
创新点1:数字化辅助自动校准环路(方法创新) - 提出了一种基于数字辅助的自动校准环路,显著降低了校准成本,通过数字控制实现高精度校准,使VREF的σ/µ变化从±0.53%降至±0.12%。
创新点2:自动单点修调方法(方法创新) - 设计了一种自动单点修调方法,利用电流数字模拟转换器(IDAC)实现快速校准,解决了传统修调方法在多温度点下的不足,提升了温度稳定性(TC为22.3 ppm/°C)。
创新点3:同时缓解VEB和ΔVEB变化(电路创新) - 通过理论分析BJT的工艺变化对VEB和ΔVEB的影响,提出了一种新型校准电路,有效减少了VREF及其温度系数的残余误差,提升了整体精度。
创新点4:低功耗设计(系统创新) - 在65 nm CMOS工艺下实现亚微瓦级功耗(Sub-µW),同时保持优异的线调整率(1.26 mV/V),适用于低功耗物联网设备。
Abstract
This article presents an auto-calibration technique for current-based bandgap voltage references (BGRs), based on a digitally-assisted auto-calibration loop for calibration cost reduc- tion. We first present a theoretical study of the process variation induced VEB and 1VEB variations in the BJT, which contribute to residual errors in the reference voltage (VREF) and its temperature coefficient (TC) after applying conventional one-point trimming. Based on the study, we further propose an automatic one-point trimming methodology using a current digital-to-analog con- verter (IDAC), which can simultaneously relax the VEB and 1VEB variations, resulting in a small drift in both VREF and its TC after calibration. Fabricated in 65 nm standard CMOS, the proposed auto-calibrated BGR achieves a measured TC of 22.3 ppm/ ◦C at 1.2 V supply within −40 ◦C to 120 ◦C. The line regulation is 1.26 mV/V or 0.13%/V from 1.2 to 2.5 V . Based on ten-chip measurement results, the achieved σ /µ variation in VREF improves from ±0.53% to ±0.12% within the entire temperature spectrum after applying the proposed auto-calibration technique at 27 ◦C.