A 14–32 GHz SiGe-BiCMOS Gilbert-Cell Frequency Doubler With Self-Adjusted Reduced Duty-Cycle Performance Enhancement

Abstract

A novel approach to implement mixer-based fre- quency doublers is proposed in this article. By driving the two ports of a Gilbert-cell with in-phase signals, but reduc- ing the switching-quad duty-cycle, the output current assumes square-wave shape at twice the input frequency, with enhanced harmonic conversion gain and free of DC offset. By avoiding the need of quadrature-signals generation, commonly required in multiplier-based frequency doublers, the performance advan- tage of the proposed approach is intrinsically broadband. The switching-quad duty-cycle is reduced by biasing the switching-quad transistors with a DC offset automatically reg- ulated by a simple low-frequency loop. The article includes a detailed discussion of the operation principle, an analysis of the robustness to impairments, and thorough design considerations. The performance of the proposed architecture is finally compared against a conventional quadrature-driven Gilbert-cell doubler designed and implemented with the same technology. Realized in a SiGe-BiCMOS process, and operating at 1.5 V supply voltage, the doubler achieves state-of-the-art conversion gain (6 dB), Psat (5.7 dBm) and efficiency (17%). The operation bandwidth, of more than one octave (14–32 GHz), demonstrates a remarkable improvement against previous works.