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JSSC 2024第3期Other65nm

A 72-Channel Resistive-and-Capacitive Sensor-Interface Chip With Noise-Orthogonalizing and Pad-Sharing Techniques

提出一种72通道电阻电容传感器接口芯片,采用噪声正交化和焊盘共享技术,实现高效低功耗传感。
65nm CMOS, 0.74 µW/Channel, 0.038 mm²/Channel, 286 Ω, 162 fF
传感器接口噪声正交化焊盘共享低功耗高能效
噪声正交化技术消除信号频率量化噪声
焊盘共享技术减少I/O焊盘数量
高能效设计(19.1 pJ/step/channel)
Abstract
The growing trend of the Internet of Things (IoT) involves trillions of sensors in various applications. An extensive array of parameters need to be gathered concurrently with high-precision, low-cost, and low-power sensor nodes, such as resistive (R) and capacitive (C) sensors. Single-chip channel fusion can be an effective solution, while it is challenging to suppress the noise and integrate massive I/O pads. However, conventional oversampling noise-shaping methods increase power consumption, which fails to meet the demand of long-term mon- itoring applications. In addition, existing R/C sensor-interface chips require a pair of I/O pads for each sensor, where the pad frame dominates the overall chip area in massive-channel integration. In this work, we demonstrate a 72-channel R&C sensor-interface chip for proximity-and-temperature sensing. A noise-orthogonalizing technique is proposed to eliminate the quantization noise at the signal frequencies, achieving an energy efficiency of 19.1 pJ/step/channel. Moreover, a pad-sharing tech- nique is proposed to reduce the number of I/O pads by half, enabling 72 sensors to be read by 36 pairs of I/O pads. The chip is fabricated by 65-nm CMOS technology, and measurement results show resolutions of 286  and 162 fF, respectively. The power consumption and die area are reduced to 0.74 µW/Channel and 0.038 mm 2/Channel, respectively.