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JSSC 2024第3期Power ManagementCharge PumpPLL

A Sub-50-fsrms Jitter Fractional- N CPPLL Based on a Dual-DTC-Assisted Time-Ampl

提出了一种基于双DTC辅助时间放大PFD的24-28GHz亚50fs抖动分数N CPPLL。
37.1 fs rms jitter (integer-N), 45.6 fs rms jitter (fractional-N)
分数N CPPLL双DTC时间放大PFD量化误差非线性补偿
▸双DTC辅助时间放大PFD结构
▸可级联DTC齿轮估计和非线性补偿算法
▸同时抑制CP带内噪声和量化误差
Abstract
A 24–28-GHz sub-50-fs rms jitter fractional- N charge pump phase-locked loop (CPPLL) is presented in this work. A dual-digital-to-time converter (DTC)-assisted time-amplifying phase-frequency detector (TAPFD) structure is proposed to suppress the in-band noise of charge pump (CP) and cancel the quantization error (QE) simultaneously while keeping low power consumption. Moreover, a cascadable DTC gear estimation and nonlinearity compensation algorithm (NLC) is also proposed to mitigate the fracti