JSSC 2024第3期Digital Circuits16nm

Amber A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Fle

Amber是一款16nm SoC，集成粗粒度可重构阵列，用于加速密集线性代数应用。

538 INT16 GOPS/W, 483 BFloat16 GFLOPS/W

系统级芯片粗粒度可重构阵列密集线性代数动态部分重配置能效优化

▸动态部分重配置（DPR）技术提升资源利用率

▸支持仿射访问模式的流式内存控制器

▸低开销超越和复数算术运算

Abstract

Amber is a system-on-chip (SoC) with a coarse- grained reconfigurable array (CGRA) for acceleration of dense linear algebra applications, such as machine learning (ML), image processing, and computer vision. It is designed using an agile accelerator–compiler codesign flow; the compiler updates automatically with hardware changes, enabling con- tinuous application-level evaluation of the hardware–software system. To increase hardware utilization and minimize recon- figurability overhead, Amber fe