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DIMCA An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate
提出一种新型数字内存计算宏DIMCA，通过近似算术提高面积效率，同时保持计算密度。
327 kb/mm², 458–990 TOPS/W, 8.27–392 TOPS/mm², 90.41% accuracy for CIFAR-10
数字内存计算近似算术面积效率计算密度神经网络
▸采用近似算术硬件提高面积效率
▸提出近似感知训练模型和定制数字格式以补偿精度损失
▸在28nm CMOS工艺中实现两种版本DIMCA1和DIMCA2
Abstract
Recent SRAM-based in-memory computing (IMC)
hardware demonstrates high energy efficiency and throughput
for matrix–vector multiplication (MVM), the dominant kernel
for deep neural networks (DNNs). Earlier IMC macros have
employed analog-mixed-signal (AMS) arithmetic hardware. How-
ever, those so-called AIMCs suffer from process, voltage, and
temperature (PVT) variations. Digital IMC (DIMC) macros,
on the other hand, exhibit better robustness against PVT
variations, but they tend to require more