A 1024-Channel 268-nW/Pixel 36 × 36 µm2/ Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain–Computer Interfaces

Abstract

This article presents a data-compressive neu- ral recording IC for single-cell resolution high-bandwidth brain–computer interfaces (BCIs). The IC features wired- OR lossy compression during digitization, thus preventing data deluge and massive data movement. By discarding unwanted baseline samples of the neural signals, the output data rate is reduced by 146× on average while allowing the reconstruction of spike samples. The recording array consists of pulse-position Manuscript received 31 August 2023; revised 14 November 2023; accepted 9 December 2023. Date of publication 29 December 2023; date of current version 28 March 2024. This article was approved by Asso- ciate Editor Mototsugu Hamada. This work was supported in part by the Wu Tsai Neurosciences Institute, Stanford University; and in part by the Stanford Nanofabrication Facility and the National Institutes of Health (NIH) under Grant EY021271 and Grant EY032900. (Corresponding author: Moonhyung Jang.) Moonhyung Jang, Pietro Caragiulo, Athanasios T. Ramkaj, A. J. Phillips, Nicholas Vitale, Pulkit Tandon, and Pumiao Yan are with the Department of Electrical Engineering, Stanford University, Stanford, CA 94305 USA (e-mail: moon90@stanford.edu). Maddy Hays is with the Department of Bioengineering, Stanford University, Stanford, CA 94305 USA. Wei-Han Yu and Pui-In Mak are with the Institute of Microelectronics, University of Macau, Macau, China. Changuk Lee is with the Department of Electrical Engineering and Computer Scie