JSSC 2024第4期Data Converters65nmDACNeural Network Accelerator

A 1865 fJConv-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dyn

一种高效能电平交叉ADC，适用于稀疏信号数字化，采用动态自偏置比较器和新型DAC架构。

65nm CMOS, 64dB SNDR, 20kHz带宽, 1.8fJ/conv.-step

电平交叉ADC动态自偏置稀疏信号生物医学应用能效优化

▸创新点1：动态自偏置比较器（电路创新） - 该比较器在输入电压远离决策阈值时仅需极小电流，显著降低功耗，实现了1.8 fJ/conv.-step的超高能效，尤其适合稀疏信号处理。

▸创新点2：无信号衰减DAC架构（系统创新） - 通过改进传统LC ADC中的DAC设计，避免了信号衰减问题，将SNDR提升至64 dB，增强了信号保真度。

▸创新点3：稀疏信号高效数字化（方法创新） - 针对生物电位等稀疏信号优化采样策略，实测FoM低至0.9 fJ/conv.-step，为生物医学应用提供超低功耗解决方案。

▸创新点4：微型化集成（工艺创新） - 采用65nm CMOS工艺实现0.0045 mm²的芯片面积，在保持高性能的同时极大提升了空间利用率。

Abstract

This work presents a power-efficient level crossing (LC) ADC designed to digitize sparse signals. It uses dynamically self-biased comparators, which require minimal current when the input voltage is far from a decision threshold. It also uses a DAC architecture which avoids the signal attenua- tion commonly present in prior LC ADC works, improving the achievable SNDR. The prototype is designed and implemented in a 65-nm CMOS technology, and occupies an area of 0.0045 mm 2. In a 20 kHz bandwidth,