← 返回 JSSC 论文列表
📄 下载 JSSC 原文 PDF
JSSC 2024第4期Power Management

A 187-dB FoM S Power-Efficient Second-Order Highpass 16 Capacitance-to-Digital Converter

提出一种高分辨率能效高的二阶高通16位电容数字转换器架构。
5.85 aF rms分辨率, 46 fJ/转换步, FoMS 187.4 dB
电容数字转换器高通调制器高分辨率能效传感器接口
创新点1:二阶高通16位调制器设计(方法创新)。该设计通过优化调制器架构,显著提升了噪声抑制能力和信号处理效率,实现了187.4 dB的FoMS指标,较现有技术提升2倍以上。
创新点2:连续时间电容电压转换器(电路创新)。采用CT CVC技术,实现了高精度的电容信号转换,同时降低了功耗,达到5.85 aF rms的超高分辨率。
创新点3:高功率效率解决方案(系统创新)。通过整合二阶调制器和CT CVC,系统整体功耗仅为46 fJ/conversion-step,为高分辨率电容传感应用提供了高效能方案。
创新点4:FoMS与FoMW的协同优化(性能创新)。在提升FoMS至187.4 dB的同时,保持了FoMW的竞争力,实现了性能与能效的平衡。
Abstract
The escalating demand for high-resolution sensor interface systems, driven by the proliferation of the Inter- net of Things (IoT) and wearable smart devices, has led to the widespread use of capacitive sensing transducers. These transducers are valued for their low-noise and low-power charac- teristics, making them suitable for various applications, including environmental and biomedical sensing. However, designing a high-resolution capacitive sensor interface system while main- taining power efficiency remains challenging. This article proposes a high-resolution energy-efficient highpass (HP) 16 capacitance-to-digital converter (CDC) architecture. The archi- tecture incorporates a 2nd-order HP 16 modulator (16M) and a continuous-time capacitance-to-voltage converter (CT CVC). The proposed CDC achieves an excellent capacitance resolution of 5.85 aF rms, with a power efficiency of 46 fJ/conversion-step and an FoMS of 187.4 dB. The HP 16M, designed with superior power efficiency, offers a promising solution for high-resolution capacitive sensor applications. Compared to state-of-the-art, the proposed CDC achieves more than 2× FoMS improvement while maintaining competitive FoM W.