JSSC 2024第4期Memory3nm FinFETSRAM

A 3-nm FinFET 27.6-Mbit/mm 2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking Yumito Aoyagi

提出一种3nm FinFET 6T SRAM宏，采用远端预充电和弱位跟踪电路，提升读写速度并扩展工作电压范围。

0.48-1.2V宽电压工作，1.9GHz@0.75V，27.6Mbit/mm²密度

6T SRAMFinFET预充电电路弱位跟踪高密度存储

▸创新点1：远端预充电电路（FPC）是一种电路创新，通过将预充电电路放置在远离存储单元的位置，显著减少了预充电周期时间，从而降低了整体写入周期时间，提高了SRAM的操作频率。

▸创新点2：弱位跟踪电路（WB）是一种方法创新，通过动态跟踪和调整感应使能时序，增强了在不同电源电压下的时序跟踪能力，从而提高了读取周期的稳定性和速度，特别是在低电压操作下。

▸创新点3：高密度276Mbit/mm²设计是一种系统创新，通过优化3-nm FinFET工艺下的存储单元布局和互连技术，实现了极高的存储密度，同时保持了高性能和低功耗，达到了行业领先的比特密度。

▸创新点4：宽电压范围操作（0.48–1.2 V）是一种电路创新，通过优化电源管理和信号路径设计，使得SRAM能够在极低电压（0.48V）到高电压（1.2V）范围内稳定工作，显著提升了能效比和适应性。

Abstract

A 3-nm FinFET single-port (SP) 6T SRAM macro is proposed that utilizes a far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuits can decrease write cycle time by decreasing the pre-charge period and engaging read cycle time by enhancing the trackability of sense enable timing over supply voltage. A prototype of the 434-kbit SP SRAM macro on 3-nm FinFET technology was designed and fabricated. The bit density is 27.6 Mbit/mm 2 and it achieved an operation of 1.9 GHz at 0.75 V and 85 ◦C, which is 35% faster than conventional performance. Measured silicon data demonstrate a wide operating voltage range of 0.48–1.2 V . This proposal has also achieved the best figure of merit (FoM) compared to other works, as defined by density × access per second (APS)/supply voltage ( VDD).