JSSC 2024第4期Data Converters65nmDelta-Sigma ADC

A Highly Digital 143.2-dB DR Sub-1 ◦ Phase Error Impedance Monitoring IC With Pulsewidth

一款高动态范围、低相位误差的数字阻抗监测芯片

143.2 dB动态范围, 0.675°相位误差, 310.9 µW功耗, 1.2V供电

阻抗监测数字架构PWMΔΣ调制器高动态范围

▸创新点1：采用PWM前端实现高动态范围（系统创新）。通过脉冲宽度调制（PWM）前端对激励信号进行编码，显著提升了系统的动态范围（>140 dB），同时降低了相位误差（<1°），解决了传统模拟前端在宽动态范围和高精度之间的矛盾。

▸创新点2：使用连续时间ΔΣ调制器提高精度（电路创新）。通过两个连续时间（CT）ΔΣ调制器对I/Q信号进行数字化处理，结合数字控制振荡器（DCO）技术，实现了17.7 fF rms的高分辨率电容检测，显著提升了系统的测量精度。

▸创新点3：高度数字化的架构提升能效和面积效率（系统创新）。通过将大部分模拟电路替换为数字模块（如PWM和DCO-based ΔΣ调制器），在65-nm CMOS工艺下实现了0.21 mm²的小面积和310.9 µW的低功耗，兼顾了高性能与低成本。

▸创新点4：方波激励与PWM结合的混合信号处理（方法创新）。尽管采用方波激励器，但通过PWM前端实现了0.675°的超低相位误差，突破了传统方波激励在相位精度上的限制，为阻抗监测提供了新的设计思路。

Abstract

This article presents a highly digital impedance monitoring IC that achieves a wide dynamic range (DR) (>140 dB), small area (∼0.2 mm 2), and small phase error (<1 ◦). It consists of a square-wave current stimulator, a pulsewidth modulation (PWM) frontend, and two continuous-time (CT) delta-sigma (16 ) modulators. The stimulated signal is encoded using the PWM frontend and the complex impedance information can be extracted by in (I) and quadrature (Q) demodulation. Each output can then be digitized using a second-order digitally controlled oscillator (DCO)-based CT 16 modulator. This highly digital architecture enhances energy and area efficiencies. The prototype IC occupies only 0.21 mm 2 in a 65-nm CMOS process. It achieves a DR of 143.2 dB and a resolution of 17.7 fF rms for capacitance detection within a conversion time of 16 ms. Despite the use of a square-wave stimulator, the PWM frontend allows achieving a small phase error of 0.675 ◦, while consuming only 310.9 µW from a 1.2-V supply.