JSSC 2024第4期Data Converters28nmSAR ADCDelta-Sigma ADC

An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer

提出一种结合VCO-CTDSM与NS-SAR量化器的混合架构，通过AAF实现高阶噪声传递函数。

28nm CMOS, 1-MHz带宽, 100 MS/s, 1.62 mW功耗

VCO-CTDSMNS-SAR量化器抗混叠滤波器噪声传递函数混合架构

▸VCO-CTDSM与NS-SAR量化器混合架构

▸AAF桥接VCO前端与NS-SAR量化器

▸无需校准或系数调谐

Abstract

This work introduces a new hybrid architec- ture combining a voltage-controlled oscillator (VCO)-based continuous-time (CT) delta-sigma modulator (DSM) with a noise-shaping (NS) successive approximation register (SAR) quantizer. The key innovation is an anti-aliasing filter (AAF) that bridges the VCO front-end with the NS-SAR quantizer, enabling the time-domain information to be directly sampled as the voltage-domain information. The hybrid architecture provides a high-order noise transfer funct