JSSC 2024第4期Analog Circuits180nm

Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-U

介绍超截止晶体管技术和皮瓦级功耗模拟电路模块，应用于无电池光唤醒接收器。

180-nm CMOS, 37-dB dc gain, 22.4-Hz gain-bandwidth, 25-µV input-referred noise, 6.87 pW

超截止晶体管皮瓦级功耗模拟电路光唤醒接收器无电池

▸超截止晶体管操作（VGS < 0 V）：通过将晶体管偏置在超截止区（VGS < 0 V），显著降低漏电流至皮瓦级，突破了传统亚阈值设计的功耗极限，实现37-dB直流增益与6.87 pW总功耗的平衡。

▸皮瓦级功耗模拟电路模块：提出单端/全差分OTA架构，在180nm CMOS工艺下达成22.4-Hz增益带宽积与25µV输入参考噪声，首次将模拟模块功耗压缩至皮瓦级（78-pW系统级验证），支持无电池工作。

▸无电池光唤醒接收器（WuRx）系统设计：利用1mm²太阳能电池在1 lx（月光级）光照下实现近100%持续运行，无需储能元件，为LiFi应用提供零功耗解决方案，系统总功耗仅78 pW。

▸自供能电路拓扑创新：结合超截止操作与动态偏置技术，消除传统唤醒电路的静态功耗，实现光能-信号直接转换的极低噪声（<30µV）信号链，扩展了能量采集系统的光照下限。

Abstract

Techniques to reduce power well below regular transistor leakage in analog circuits are introduced. Key building blocks with super-cutoff transistor operation (i.e., VGS < 0 V) and pW-range consumption are demonstrated. Single-ended and fully differential versions of operational transconductance amplifiers (OTAs) are presented in several configurations, achieving 37-dB dc gain, 22.4-Hz gain-bandwidth product, and 25-µV input- referred noise at 6.87 pW in 180-nm CMOS. For system-level demonstrati