JSSC 2024第5期Other65nm

A Low-Noise Dual-Path Self-Interference Cancellation Architecture for Watt-Level TX Power Handling in Simultaneous Transmit and Receive

提出一种新型双路径自干扰消除方案，支持瓦级功率处理，噪声和线性度表现优异。

65nm CMOS, 600 MHz, 45-dB SIC, 12-dBm RX SI peak power, 4-dB NF degradation, 207-mW power consumption

自干扰消除全双工频率分集双工噪声消除高功率处理

▸创新点1：双路径自干扰消除架构（系统创新）。通过主路径的频率转换自干扰消除器和辅助路径的频率转换噪声消除路径，实现了对高功率自干扰的有效抑制，同时降低了噪声和失真，支持全双工和频分双工方案。

▸创新点2：频率转换噪声消除技术（电路创新）。采用频率转换技术将噪声和失真从主消除器中分离，并通过辅助路径进行消除，显著降低了噪声系数（仅增加4dB NF），提升了系统灵敏度。

▸创新点3：高功率自干扰处理能力（性能创新）。在600 MHz频率下，实现了12dBm峰值功率（9dBm平均功率）的自干扰消除，支持高达30dBm的发射功率处理能力，隔离度超过15dB，性能优于现有方案8倍。

▸创新点4：宽频带操作能力（系统创新）。该架构在0.5至1.3 GHz的宽频带范围内均能有效工作，适用于多种通信频段，增强了系统的灵活性和适用性。

Abstract

Mitigating self-interference (SI) is vital for advanc- ing simultaneous transmit and receive (STAR) systems. The noise and linearity of the canceller impose limitations on SI power handling. This article proposes a novel dual-path SI cancelling scheme for high-power SI handling. The proposed approach breaks self-interference cancellation (SIC) tradeoffs between operating frequency, SI power handling, and canceller noise/distortion by using a frequency-translated (FT) SI canceller and an auxiliary FT noise-cancelling (NC) path that cancels the noise/distortion from the primary canceller. This approach can work well for both full-duplex (FD) and frequency-division duplex (FDD) schemes. The 65-nm CMOS implementation achieves ∼45-dB SIC for 12-dBm receiver (RX) SI peak power (9-dBm avg.) with only 4-dB noise figure (NF) degradation and 207-mW power consumption at 600 MHz. The SIC approach enables a blocker-1 dB with respect to SI of >16 dBm (8× higher than prior work) while operating from 0.5 to 1.3 GHz. Therefore, this implementation can support watt-level SI power handling with transmitter (TX)–RX isolation >15 dB. This is demonstrated through measurements that show 30-dBm TX power handling with 22-dB initial isolation from the circulator.