Abstract
This article presents a capacitive isolated dc–dc converter with both the receiver (RX) and transmitter (TX) chips designed and verified in a standard 180-nm CMOS process with measurement results. This work achieves the following features. First, much higher efficiency, by using capacitive power links instead of low-quality micro-transformers and switching at a relatively lower frequency near resonance. Measurement shows a 68% peak efficiency, which is 15% higher than state-of-the-art miniature designs and is higher over almost the entire loading range. Second, RX local voltage and TX global power regu- lations are achieved with through-power-link feedback, neither using an extra pair of capacitors nor transformers. Third, the voltage-mode hysteretic control achieves a much faster transient response compared with previous works, with a simpler system complexity and neither small-signal bandwidth limitation nor stability concerns. Fourth, a two-layer “analog-keying” and “error-recovery” common-mode transient (CMT) immune strat- egy is introduced, achieving a ±8-kV CMT immunity (CMTI) measured in closed-loop operation. Fifth, reconfigurability to extend the power capacity with a shared TX chip, with measured 414-/828-mW capacity in one-/two-phase configuration. Sixth, low cost and high component compatibility, with measurements using different LC combinations, including high voltage (HV) capac- itors with different dielectrics, voltage ratings, and footprints, and miniature 040