An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update

Abstract

Computing-in-memory (CIM) chips have demon- strated the potential high energy efficiency for low-power neural network (NN) processors. Even with energy-efficient CIM macros, the existing system-level CIM chips still lack deep exploration on sparsity and large models, which prevents a higher system energy efficiency. This work presents a CIM NN processor with more sufficient support of sparsity and higher utilization rate. Three key innovations are proposed. First, a set-associate blockwise sparsity strategy is designed, which simultaneously saves execution time, power, and storage space. Second, a ping-pong weight update mechanism is proposed for a higher utilization rate, enabling simultaneous execution of CIM and write operations. Third, an efficient CIM macro is imple- mented with adaptive analog-digital converter (ADC) precision for better sparsity utilization and performance-accuracy trade- off. The 65-nm fabricated chip shows 9.5-TOPS/W system energy efficiency at 4-bit precision, with 6.25× actual improvement Manuscript received 19 June 2022; revised 15 December 2022, 16 May 2023, 26 July 2023, and 20 September 2023; accepted 9 October 2023. Date of publication 30 October 2023; date of current version 25 April 2024. This article was approved by Associate Editor Kathryn Wilcox. This work was supported in part by the National Key Research and Development Program under Grant 2018YFA0701500, in part by NSFC under Grant 61934005 and Grant 62204256, in part by the Beijing No