An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwis

Abstract

Computing-in-memory (CIM) chips have demon- strated the potential high energy efficiency for low-power neural network (NN) processors. Even with energy-efficient CIM macros, the existing system-level CIM chips still lack deep exploration on sparsity and large models, which prevents a higher system energy efficiency. This work presents a CIM NN processor with more sufficient support of sparsity and higher utilization rate. Three key innovations are proposed. First, a set-associate blockwise spars